Category: tsmc
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TSMC Unveils A13 Process: Next-Gen AI and HPC Silicon Innovation
Insights: TSMC has unveiled its latest semiconductor process technology, the A13 node, at the 2026 North America Technology Symposium held in Santa Clara, California. This new process is a direct shrink of the previously announced A14 node, delivering a 6% reduction in chip area, which translates to more compact and efficient designs. These improvements primarily
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Cadence and TSMC Forge AI Chip Design Breakthroughs
Insights: Cadence and TSMC advance AI and HPC chip design with AI-driven automation and IP. Support for TSMC’s latest process nodes including N3, N2, A16, and upcoming A14 PDK. Enhanced 3D-IC design productivity enabled by Cadence solutions integrated with TSMC’s 3DFabric. New silicon-proven IP such as HBM4, LPDDR6/5X, PCIe 7.0, and Universal Chiplet Interconnect for
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Synopsys and TSMC Drive AI Chip Innovation with Advanced EDA and IP
Insights: Synopsys continues to strengthen its partnership with TSMC to advance semiconductor innovation focused on AI and multi-die designs. Leveraging TSMC’s leading-edge processes such as N2P, A16, and future A14, Synopsys provides certified analog and digital EDA flows that optimize chip performance, power efficiency, and scalability. Their 3DIC Compiler platform supports complex 3D integration technologies